Merge pull request #9079 from Morph1984/unknown-unkowns
general: Fix spelling
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commit
2f37c7948f
@ -14,7 +14,7 @@ enum class CameraAmbientNoiseLevel : u32 {
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Low,
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Medium,
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High,
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Unkown3, // This level can't be reached
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Unknown3, // This level can't be reached
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};
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// This is nn::irsensor::CameraLightTarget
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@ -75,9 +75,9 @@ enum class IrCameraStatus : u32 {
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enum class IrCameraInternalStatus : u32 {
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Stopped,
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FirmwareUpdateNeeded,
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Unkown2,
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Unkown3,
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Unkown4,
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Unknown2,
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Unknown3,
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Unknown4,
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FirmwareVersionRequested,
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FirmwareVersionIsInvalid,
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Ready,
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@ -121,20 +121,20 @@ enum class IrSensorFunctionLevel : u8 {
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// This is nn::irsensor::MomentProcessorPreprocess
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enum class MomentProcessorPreprocess : u32 {
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Unkown0,
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Unkown1,
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Unknown0,
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Unknown1,
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};
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// This is nn::irsensor::PackedMomentProcessorPreprocess
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enum class PackedMomentProcessorPreprocess : u8 {
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Unkown0,
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Unkown1,
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Unknown0,
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Unknown1,
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};
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// This is nn::irsensor::PointingStatus
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enum class PointingStatus : u32 {
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Unkown0,
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Unkown1,
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Unknown0,
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Unknown1,
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};
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struct IrsRect {
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@ -2118,7 +2118,7 @@ void Hid::WritePalmaWaveEntry(Kernel::HLERequestContext& ctx) {
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ASSERT_MSG(t_mem->GetSize() == 0x3000, "t_mem has incorrect size");
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LOG_WARNING(Service_HID,
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"(STUBBED) called, connection_handle={}, wave_set={}, unkown={}, "
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"(STUBBED) called, connection_handle={}, wave_set={}, unknown={}, "
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"t_mem_handle=0x{:08X}, t_mem_size={}, size={}",
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connection_handle.npad_id, wave_set, unknown, t_mem_handle, t_mem_size, size);
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@ -37,10 +37,10 @@ private:
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u8 pointing_status;
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INSERT_PADDING_BYTES(3);
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u32 unknown;
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float unkown_float1;
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float unknown_float1;
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float position_x;
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float position_y;
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float unkown_float2;
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float unknown_float2;
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Core::IrSensor::IrsRect window_of_interest;
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};
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static_assert(sizeof(PointingProcessorMarkerData) == 0x20,
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@ -18,7 +18,7 @@ class DescriptorTable {
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public:
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explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {}
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[[nodiscard]] bool Synchornize(GPUVAddr gpu_addr, u32 limit) {
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[[nodiscard]] bool Synchronize(GPUVAddr gpu_addr, u32 limit) {
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[[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) {
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return false;
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}
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@ -193,11 +193,11 @@ void TextureCache<P>::SynchronizeGraphicsDescriptors() {
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const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding;
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const u32 tic_limit = maxwell3d->regs.tex_header.limit;
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const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit;
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if (channel_state->graphics_sampler_table.Synchornize(maxwell3d->regs.tex_sampler.Address(),
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if (channel_state->graphics_sampler_table.Synchronize(maxwell3d->regs.tex_sampler.Address(),
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tsc_limit)) {
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channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
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}
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if (channel_state->graphics_image_table.Synchornize(maxwell3d->regs.tex_header.Address(),
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if (channel_state->graphics_image_table.Synchronize(maxwell3d->regs.tex_header.Address(),
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tic_limit)) {
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channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
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}
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@ -209,10 +209,10 @@ void TextureCache<P>::SynchronizeComputeDescriptors() {
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const u32 tic_limit = kepler_compute->regs.tic.limit;
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const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit;
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const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address();
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if (channel_state->compute_sampler_table.Synchornize(tsc_gpu_addr, tsc_limit)) {
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if (channel_state->compute_sampler_table.Synchronize(tsc_gpu_addr, tsc_limit)) {
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channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
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}
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if (channel_state->compute_image_table.Synchornize(kepler_compute->regs.tic.Address(),
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if (channel_state->compute_image_table.Synchronize(kepler_compute->regs.tic.Address(),
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tic_limit)) {
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channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
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}
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