Merge pull request #3208 from ReinUsesLisp/vk-shader-decompiler
vk_shader_decompiler: Add tessellation and misc changes
This commit is contained in:
commit
6edadef96d
2
externals/sirit
vendored
2
externals/sirit
vendored
@ -1 +1 @@
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Subproject commit f7c4b07a7e14edb1dcd93bc9879c823423705c2e
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Subproject commit e1a6729df7f11e33f6dc0939b18995a57c8bf3d8
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@ -98,10 +98,11 @@ union Attribute {
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BitField<20, 10, u64> immediate;
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BitField<20, 10, u64> immediate;
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BitField<22, 2, u64> element;
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<24, 6, Index> index;
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BitField<31, 1, u64> patch;
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BitField<47, 3, AttributeSize> size;
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BitField<47, 3, AttributeSize> size;
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bool IsPhysical() const {
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bool IsPhysical() const {
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return element == 0 && static_cast<u64>(index.Value()) == 0;
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return patch == 0 && element == 0 && static_cast<u64>(index.Value()) == 0;
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}
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}
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} fmt20;
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} fmt20;
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@ -1915,6 +1915,10 @@ private:
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return {};
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return {};
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}
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}
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Expression InvocationId(Operation operation) {
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return {"gl_InvocationID", Type::Int};
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}
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Expression YNegate(Operation operation) {
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Expression YNegate(Operation operation) {
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return {"y_direction", Type::Float};
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return {"y_direction", Type::Float};
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}
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}
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@ -2153,6 +2157,7 @@ private:
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&GLSLDecompiler::EmitVertex,
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&GLSLDecompiler::EmitVertex,
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&GLSLDecompiler::EndPrimitive,
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&GLSLDecompiler::EndPrimitive,
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&GLSLDecompiler::InvocationId,
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&GLSLDecompiler::YNegate,
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&GLSLDecompiler::YNegate,
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&GLSLDecompiler::LocalInvocationId<0>,
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&GLSLDecompiler::LocalInvocationId<0>,
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&GLSLDecompiler::LocalInvocationId<1>,
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&GLSLDecompiler::LocalInvocationId<1>,
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File diff suppressed because it is too large
Load Diff
@ -5,29 +5,28 @@
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#pragma once
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#pragma once
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#include <array>
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#include <array>
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#include <bitset>
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#include <memory>
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#include <memory>
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#include <set>
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#include <set>
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#include <type_traits>
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#include <utility>
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#include <utility>
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#include <vector>
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#include <vector>
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#include <sirit/sirit.h>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/shader/shader_ir.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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class ShaderIR;
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}
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namespace Vulkan {
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namespace Vulkan {
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class VKDevice;
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class VKDevice;
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}
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}
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namespace Vulkan::VKShader {
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namespace Vulkan {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using TexelBufferEntry = VideoCommon::Shader::Sampler;
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using SamplerEntry = VideoCommon::Shader::Sampler;
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using SamplerEntry = VideoCommon::Shader::Sampler;
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using ImageEntry = VideoCommon::Shader::Image;
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constexpr u32 DESCRIPTOR_SET = 0;
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constexpr u32 DESCRIPTOR_SET = 0;
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@ -46,39 +45,74 @@ private:
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class GlobalBufferEntry {
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class GlobalBufferEntry {
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public:
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public:
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explicit GlobalBufferEntry(u32 cbuf_index, u32 cbuf_offset)
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constexpr explicit GlobalBufferEntry(u32 cbuf_index, u32 cbuf_offset, bool is_written)
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: cbuf_index{cbuf_index}, cbuf_offset{cbuf_offset} {}
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: cbuf_index{cbuf_index}, cbuf_offset{cbuf_offset}, is_written{is_written} {}
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u32 GetCbufIndex() const {
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constexpr u32 GetCbufIndex() const {
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return cbuf_index;
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return cbuf_index;
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}
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}
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u32 GetCbufOffset() const {
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constexpr u32 GetCbufOffset() const {
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return cbuf_offset;
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return cbuf_offset;
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}
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}
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constexpr bool IsWritten() const {
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return is_written;
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}
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private:
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private:
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u32 cbuf_index{};
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u32 cbuf_index{};
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u32 cbuf_offset{};
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u32 cbuf_offset{};
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bool is_written{};
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};
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};
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struct ShaderEntries {
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struct ShaderEntries {
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u32 const_buffers_base_binding{};
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u32 NumBindings() const {
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u32 global_buffers_base_binding{};
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return static_cast<u32>(const_buffers.size() + global_buffers.size() +
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u32 samplers_base_binding{};
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texel_buffers.size() + samplers.size() + images.size());
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}
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std::vector<ConstBufferEntry> const_buffers;
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std::vector<ConstBufferEntry> const_buffers;
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std::vector<GlobalBufferEntry> global_buffers;
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std::vector<GlobalBufferEntry> global_buffers;
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std::vector<TexelBufferEntry> texel_buffers;
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std::vector<SamplerEntry> samplers;
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std::vector<SamplerEntry> samplers;
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std::vector<ImageEntry> images;
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std::set<u32> attributes;
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std::set<u32> attributes;
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std::array<bool, Maxwell::NumClipDistances> clip_distances{};
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std::array<bool, Maxwell::NumClipDistances> clip_distances{};
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std::size_t shader_length{};
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std::size_t shader_length{};
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Sirit::Id entry_function{};
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bool uses_warps{};
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std::vector<Sirit::Id> interfaces;
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};
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};
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using DecompilerResult = std::pair<std::unique_ptr<Sirit::Module>, ShaderEntries>;
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struct Specialization final {
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u32 base_binding{};
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DecompilerResult Decompile(const VKDevice& device, const VideoCommon::Shader::ShaderIR& ir,
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// Compute specific
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Tegra::Engines::ShaderType stage);
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std::array<u32, 3> workgroup_size{};
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u32 shared_memory_size{};
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} // namespace Vulkan::VKShader
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// Graphics specific
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Maxwell::PrimitiveTopology primitive_topology{};
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std::optional<float> point_size{};
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std::array<Maxwell::VertexAttribute::Type, Maxwell::NumVertexAttributes> attribute_types{};
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// Tessellation specific
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struct {
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Maxwell::TessellationPrimitive primitive{};
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Maxwell::TessellationSpacing spacing{};
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bool clockwise{};
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} tessellation;
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};
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// Old gcc versions don't consider this trivially copyable.
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// static_assert(std::is_trivially_copyable_v<Specialization>);
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struct SPIRVShader {
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std::vector<u32> code;
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ShaderEntries entries;
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};
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ShaderEntries GenerateShaderEntries(const VideoCommon::Shader::ShaderIR& ir);
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std::vector<u32> Decompile(const VKDevice& device, const VideoCommon::Shader::ShaderIR& ir,
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Tegra::Engines::ShaderType stage, const Specialization& specialization);
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} // namespace Vulkan
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@ -21,6 +21,7 @@ using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Register;
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namespace {
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namespace {
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u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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switch (uniform_type) {
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switch (uniform_type) {
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case Tegra::Shader::UniformType::Single:
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case Tegra::Shader::UniformType::Single:
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@ -35,6 +36,7 @@ u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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return 1;
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return 1;
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}
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}
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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@ -196,28 +198,28 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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"Unaligned attribute loads are not supported");
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"Unaligned attribute loads are not supported");
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u64 next_element = instr.attribute.fmt20.element;
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u64 element = instr.attribute.fmt20.element;
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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auto index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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const auto StoreNextElement = [&](u32 reg_offset) {
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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const auto dest = GetOutputAttribute(static_cast<Attribute::Index>(next_index),
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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next_element, GetRegister(instr.gpr39));
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Node dest;
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if (instr.attribute.fmt20.patch) {
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const u32 offset = static_cast<u32>(index) * 4 + static_cast<u32>(element);
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dest = MakeNode<PatchNode>(offset);
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} else {
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dest = GetOutputAttribute(static_cast<Attribute::Index>(index), element,
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GetRegister(instr.gpr39));
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}
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
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bb.push_back(Operation(OperationCode::Assign, dest, src));
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bb.push_back(Operation(OperationCode::Assign, dest, src));
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// Load the next attribute element into the following register. If the element
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// Load the next attribute element into the following register. If the element to load
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// to load goes beyond the vec4 size, load the first element of the next
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// goes beyond the vec4 size, load the first element of the next attribute.
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// attribute.
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element = (element + 1) % 4;
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next_element = (next_element + 1) % 4;
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index = index + (element == 0 ? 1 : 0);
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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StoreNextElement(reg_offset);
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}
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}
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break;
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break;
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}
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}
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case OpCode::Id::ST_L:
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case OpCode::Id::ST_L:
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@ -69,6 +69,8 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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case OpCode::Id::MOV_SYS: {
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case OpCode::Id::MOV_SYS: {
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const Node value = [this, instr] {
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const Node value = [this, instr] {
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switch (instr.sys20) {
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switch (instr.sys20) {
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case SystemVariable::InvocationId:
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return Operation(OperationCode::InvocationId);
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case SystemVariable::Ydirection:
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case SystemVariable::Ydirection:
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return Operation(OperationCode::YNegate);
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return Operation(OperationCode::YNegate);
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case SystemVariable::InvocationInfo:
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case SystemVariable::InvocationInfo:
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@ -38,6 +38,9 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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// Signal the backend that this shader uses warp instructions.
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uses_warps = true;
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switch (opcode->get().GetId()) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::VOTE: {
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case OpCode::Id::VOTE: {
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const Node value = GetPredicate(instr.vote.value, instr.vote.negate_value != 0);
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const Node value = GetPredicate(instr.vote.value, instr.vote.negate_value != 0);
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@ -172,6 +172,7 @@ enum class OperationCode {
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EmitVertex, /// () -> void
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EmitVertex, /// () -> void
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EndPrimitive, /// () -> void
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EndPrimitive, /// () -> void
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InvocationId, /// () -> int
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YNegate, /// () -> float
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YNegate, /// () -> float
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LocalInvocationIdX, /// () -> uint
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LocalInvocationIdX, /// () -> uint
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LocalInvocationIdY, /// () -> uint
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LocalInvocationIdY, /// () -> uint
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@ -213,13 +214,14 @@ class PredicateNode;
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class AbufNode;
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class AbufNode;
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class CbufNode;
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class CbufNode;
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class LmemNode;
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class LmemNode;
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class PatchNode;
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class SmemNode;
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class SmemNode;
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class GmemNode;
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class GmemNode;
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class CommentNode;
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class CommentNode;
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using NodeData =
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using NodeData = std::variant<OperationNode, ConditionalNode, GprNode, ImmediateNode,
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std::variant<OperationNode, ConditionalNode, GprNode, ImmediateNode, InternalFlagNode,
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InternalFlagNode, PredicateNode, AbufNode, PatchNode, CbufNode,
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PredicateNode, AbufNode, CbufNode, LmemNode, SmemNode, GmemNode, CommentNode>;
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LmemNode, SmemNode, GmemNode, CommentNode>;
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using Node = std::shared_ptr<NodeData>;
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using Node = std::shared_ptr<NodeData>;
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using Node4 = std::array<Node, 4>;
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using Node4 = std::array<Node, 4>;
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using NodeBlock = std::vector<Node>;
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using NodeBlock = std::vector<Node>;
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@ -542,6 +544,19 @@ private:
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u32 element{};
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u32 element{};
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};
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};
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/// Patch memory (used to communicate tessellation stages).
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class PatchNode final {
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public:
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explicit PatchNode(u32 offset) : offset{offset} {}
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u32 GetOffset() const {
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return offset;
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}
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private:
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u32 offset{};
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};
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/// Constant buffer node, usually mapped to uniform buffers in GLSL
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/// Constant buffer node, usually mapped to uniform buffers in GLSL
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class CbufNode final {
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class CbufNode final {
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public:
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public:
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@ -137,6 +137,10 @@ public:
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return uses_vertex_id;
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return uses_vertex_id;
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}
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}
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bool UsesWarps() const {
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return uses_warps;
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}
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bool HasPhysicalAttributes() const {
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bool HasPhysicalAttributes() const {
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return uses_physical_attributes;
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return uses_physical_attributes;
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}
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}
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@ -415,6 +419,7 @@ private:
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bool uses_physical_attributes{}; // Shader uses AL2P or physical attribute read/writes
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bool uses_physical_attributes{}; // Shader uses AL2P or physical attribute read/writes
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bool uses_instance_id{};
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bool uses_instance_id{};
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bool uses_vertex_id{};
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bool uses_vertex_id{};
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bool uses_warps{};
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Tegra::Shader::Header header;
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Tegra::Shader::Header header;
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};
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};
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@ -7,6 +7,7 @@
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#include <variant>
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#include <variant>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/shader/node.h"
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#include "video_core/shader/shader_ir.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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namespace VideoCommon::Shader {
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