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6ced80bb47
Commit Graph

4986 Commits

Author SHA1 Message Date
bunnei
6ced80bb47 gl_rasterizer_cache: LoadGLBuffer should do a morton copy. 2018-03-22 22:54:04 -04:00
bunnei
740310113b video_core: Move MortonCopyPixels128 to utils header. 2018-03-22 22:52:40 -04:00
bunnei
8a250de987 video_core: Remove usage of PAddr and replace with VAddr. 2018-03-22 21:13:46 -04:00
bunnei
bfe45774f1 video_core: Move FramebufferInfo to FramebufferConfig in GPU. 2018-03-22 21:04:30 -04:00
bunnei
c6362543d4 gl_rasterizer: Replace a bunch of UNIMPLEMENTED with ASSERT. 2018-03-22 20:19:34 -04:00
bunnei
f707c2dac4 gl_rasterizer: Add a simple passthrough shader in lieu of shader generation. 2018-03-22 20:00:41 -04:00
bunnei
7c3a263839 gpu: Expose Maxwell3D engine. 2018-03-22 19:48:20 -04:00
bunnei
3a6604e8fa maxwell_3d: Add some format decodings and string helper functions. 2018-03-22 19:47:28 -04:00
bunnei
656de23d93 renderer: Create rasterizer and cleanup. 2018-03-22 19:46:37 -04:00
bunnei
ec5ede68e7
Merge pull request #258 from Subv/gpu_attribs 
GPU: Added vertex attrib format and triangle topology registers
 2018-03-21 19:36:06 -04:00
N00byKing
34b733e70e CMake: Set EMU_ARCH_BITS in CMakeLists.txt 2018-03-21 19:03:20 +01:00
Subv
c450d264eb GPU: Added vertex attribute format registers. 2018-03-21 09:26:47 -05:00
mailwl
6673ed1274 Service/vi: convert services to module 2018-03-21 13:09:40 +03:00
Subv
ae28a52277 GPU: Added registers for the number of vertices to render. 2018-03-20 23:28:06 -05:00
bunnei
0b3ab30762
Merge pull request #254 from bunnei/port-citra-renderer 
Port Citra OpenGL rasterizer code
 2018-03-20 21:37:43 -04:00
mailwl
dca7cfb9cf Service: add fatal:u, fatal:p services 2018-03-20 16:59:02 +03:00
bunnei
6e3222363c renderer_gl: Port boilerplate rasterizer code over from Citra. 2018-03-20 00:07:32 -04:00
bunnei
9c468e0c55 gl_shader_util: Sync latest version with Citra. 2018-03-20 00:07:31 -04:00
bunnei
d7b1ebe4a8 renderer_gl: Port over gl_shader_gen module from Citra. 2018-03-20 00:07:30 -04:00
Mat M
f4700ccabf
Merge pull request #253 from Subv/rt_depth 
GPU: Added registers for color and Z buffers.
 2018-03-19 23:37:47 -04:00
bunnei
4bdb46e4c2 renderer_gl: Port over gl_shader_decompiler module from Citra. 2018-03-19 23:14:03 -04:00
bunnei
a3e10b1a72 renderer_gl: Port over gl_rasterizer_cache module from Citra. 2018-03-19 23:14:03 -04:00
bunnei
db0cfb8e8b gl_resource_manager: Sync latest version with Citra. 2018-03-19 23:14:02 -04:00
bunnei
0e4b9cdde4 renderer_gl: Port over gl_stream_buffer module from Citra. 2018-03-19 23:14:02 -04:00
bunnei
6a0902e56d gl_state: Sync latest version with Citra. 2018-03-19 23:13:49 -04:00
Subv
7a27a11770 GPU: Added Z buffer registers to Maxwell3D's reg structure. 2018-03-19 16:55:33 -05:00
Subv
21d9519032 GPU: Added the render target (RT) registers to Maxwell3D's reg structure. 2018-03-19 16:46:29 -05:00
N00byKing
1d8b6ad13b Clang Fixes 2018-03-19 17:53:35 +01:00
N00byKing
d16e08454d
oops 2018-03-19 17:43:04 +01:00
N00byKing
0e72d0d826 More Warning cleanups 2018-03-19 17:27:04 +01:00
N00byKing
ef875d6a35 Clean Warnings (?) 2018-03-19 17:07:08 +01:00
Subv
dcae0c9a4f GPU: Added the TSC registers to the Maxwell3D register structure. 2018-03-19 00:36:25 -05:00
Subv
cff7b29bba GPU: Added the TIC registers to the Maxwell3D register structure. 2018-03-19 00:32:57 -05:00
bunnei
23a0d2d7b7
Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo 
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
 2018-03-18 22:35:47 -04:00
bunnei
2dc3a56e96
Merge pull request #250 from bunnei/buffer-dequeue-wait 
vi: TransactParcel DequeueBuffer should wait current thread
 2018-03-18 22:25:09 -04:00
bunnei
c1c92c30f9 vi: Remove DequeueBuffer and wait until next available buffer. 2018-03-18 20:56:35 -04:00
bunnei
c86af6939c hle_ipc: Add SleepClientThread to block current thread within HLE routines. 2018-03-18 20:56:34 -04:00
bunnei
2faa83ca13 hle_ipc: Use shared_ptr instead of unique_ptr to allow copies. 2018-03-18 20:56:33 -04:00
bunnei
019f1a0cf0 hle_ipc: Remove GetPointer(..) usage with WriteToOutgoingCommandBuffer. 2018-03-18 20:56:33 -04:00
bunnei
e353b9fb3d thread: Add THREADSTATUS_WAIT_HLE_EVENT, remove THREADSTATUS_WAIT_ARB. 2018-03-18 20:56:32 -04:00
Subv
03156d0c9a GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE. 
This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
 2018-03-18 19:03:40 -05:00
Subv
7b6868e908 GPU: Implement the BindStorageBuffer macro method in HLE. 
This macro binds the SSBO Info Buffer as the current ConstBuffer.
This buffer is usually bound to c0 during shader execution.
Games seem to use this macro instead of directly writing the address for some reason.
 2018-03-18 16:50:42 -05:00
Subv
85d820b1b4 GPU: Handle writes to the CB_DATA method. 
Writing to this method will cause the written value to be stored in the currently-set ConstBuffer plus CB_POS.

This method is usually used to upload uniforms or other shader-visible data.
 2018-03-18 15:23:24 -05:00
Subv
a64b936cbe GPU: Move the GPU's class constructor and destructors to a cpp file. 
This should reduce recompile times when editing the Maxwell3D register structure.
 2018-03-18 15:23:24 -05:00
Subv
aa586fa268 GPU: Store uploaded GPU macros and keep track of the number of method parameters. 2018-03-18 11:51:46 -05:00
Subv
7ac8657432 GPU: Macros are specific to the Maxwell3D engine, so handle them internally. 2018-03-18 11:51:45 -05:00
Subv
ccb8da1512 GPU: Renamed ShaderType to ShaderStage as that is less confusing. 2018-03-17 18:32:57 -05:00
Subv
88698c156f GPU: Store shader constbuffer bindings in the GPU state. 2018-03-17 18:32:57 -05:00
Subv
66dae22790 GPU: Corrected some register offsets and removed superfluous macro registers. 2018-03-17 18:32:56 -05:00
Subv
1d9d9c16e8 GPU: Make the SetShader macro call do the same as the real macro's code. 
It'll now set the CB_SIZE, CB_ADDRESS and CB_BIND registers when it's called.

Presumably this SetShader function is binding the constant shader uniforms to buffer 1 (c1[]).
 2018-03-17 18:32:55 -05:00