296 lines
8.7 KiB
C++
296 lines
8.7 KiB
C++
// Copyright 2018 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/A64/a64.h>
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#include <dynarmic/A64/config.h>
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#include "common/logging/log.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/memory.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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using Vector = Dynarmic::A64::Vector;
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class ARM_Dynarmic_Callbacks : public Dynarmic::A64::UserCallbacks {
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public:
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explicit ARM_Dynarmic_Callbacks(ARM_Dynarmic& parent) : parent(parent) {}
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~ARM_Dynarmic_Callbacks() = default;
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u8 MemoryRead8(u64 vaddr) override {
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return Memory::Read8(vaddr);
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}
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u16 MemoryRead16(u64 vaddr) override {
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return Memory::Read16(vaddr);
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}
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u32 MemoryRead32(u64 vaddr) override {
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return Memory::Read32(vaddr);
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}
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u64 MemoryRead64(u64 vaddr) override {
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return Memory::Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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return {Memory::Read64(vaddr), Memory::Read64(vaddr + 8)};
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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Memory::Write8(vaddr, value);
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}
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void MemoryWrite16(u64 vaddr, u16 value) override {
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Memory::Write16(vaddr, value);
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}
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void MemoryWrite32(u64 vaddr, u32 value) override {
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Memory::Write32(vaddr, value);
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}
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void MemoryWrite64(u64 vaddr, u64 value) override {
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Memory::Write64(vaddr, value);
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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Memory::Write64(vaddr, value[0]);
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Memory::Write64(vaddr + 8, value[1]);
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}
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void InterpreterFallback(u64 pc, size_t num_instructions) override {
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LOG_INFO(Core_ARM, "Unicorn fallback @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryReadCode(pc));
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ARM_Interface::ThreadContext ctx;
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parent.SaveContext(ctx);
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parent.inner_unicorn.LoadContext(ctx);
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parent.inner_unicorn.ExecuteInstructions(static_cast<int>(num_instructions));
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parent.inner_unicorn.SaveContext(ctx);
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parent.LoadContext(ctx);
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num_interpreted_instructions += num_instructions;
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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default:
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ASSERT_MSG(false, "ExceptionRaised(exception = {}, pc = {:X})",
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static_cast<size_t>(exception), pc);
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}
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}
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void CallSVC(u32 swi) override {
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Kernel::CallSVC(swi);
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}
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void AddTicks(u64 ticks) override {
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CoreTiming::AddTicks(ticks - num_interpreted_instructions);
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num_interpreted_instructions = 0;
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}
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u64 GetTicksRemaining() override {
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return std::max(CoreTiming::GetDowncount(), 0);
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}
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u64 GetCNTPCT() override {
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return CoreTiming::GetTicks();
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}
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ARM_Dynarmic& parent;
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size_t num_interpreted_instructions = 0;
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u64 tpidrro_el0 = 0;
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u64 tpidr_el0 = 0;
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};
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std::unique_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit() {
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const auto page_table = Core::CurrentProcess()->vm_manager.page_table.pointers.data();
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Dynarmic::A64::UserConfig config;
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// Callbacks
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config.callbacks = cb.get();
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// Memory
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config.page_table = reinterpret_cast<void**>(page_table);
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config.page_table_address_space_bits = Memory::ADDRESS_SPACE_BITS;
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config.silently_mirror_page_table = false;
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// Multi-process state
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config.processor_id = core_index;
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config.global_monitor = &exclusive_monitor->monitor;
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// System registers
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config.tpidrro_el0 = &cb->tpidrro_el0;
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config.tpidr_el0 = &cb->tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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void ARM_Dynarmic::Run() {
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ASSERT(Memory::GetCurrentPageTable() == current_page_table);
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jit->Run();
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}
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void ARM_Dynarmic::Step() {
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cb->InterpreterFallback(jit->GetPC(), 1);
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}
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ARM_Dynarmic::ARM_Dynarmic(std::shared_ptr<ExclusiveMonitor> exclusive_monitor, size_t core_index)
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: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)),
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jit(MakeJit()), exclusive_monitor{std::dynamic_pointer_cast<DynarmicExclusiveMonitor>(
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exclusive_monitor)},
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core_index{core_index} {
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ARM_Interface::ThreadContext ctx;
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inner_unicorn.SaveContext(ctx);
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LoadContext(ctx);
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PageTableChanged();
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}
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ARM_Dynarmic::~ARM_Dynarmic() = default;
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void ARM_Dynarmic::MapBackingMemory(u64 address, size_t size, u8* memory,
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Kernel::VMAPermission perms) {
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inner_unicorn.MapBackingMemory(address, size, memory, perms);
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}
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void ARM_Dynarmic::UnmapMemory(u64 address, size_t size) {
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inner_unicorn.UnmapMemory(address, size);
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}
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void ARM_Dynarmic::SetPC(u64 pc) {
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jit->SetPC(pc);
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}
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u64 ARM_Dynarmic::GetPC() const {
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return jit->GetPC();
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}
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u64 ARM_Dynarmic::GetReg(int index) const {
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return jit->GetRegister(index);
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}
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void ARM_Dynarmic::SetReg(int index, u64 value) {
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jit->SetRegister(index, value);
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}
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u128 ARM_Dynarmic::GetExtReg(int index) const {
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return jit->GetVector(index);
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}
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void ARM_Dynarmic::SetExtReg(int index, u128 value) {
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jit->SetVector(index, value);
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}
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u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const {
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UNIMPLEMENTED();
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return {};
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}
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void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
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UNIMPLEMENTED();
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}
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u32 ARM_Dynarmic::GetCPSR() const {
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return jit->GetPstate();
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}
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void ARM_Dynarmic::SetCPSR(u32 cpsr) {
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jit->SetPstate(cpsr);
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}
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u64 ARM_Dynarmic::GetTlsAddress() const {
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return cb->tpidrro_el0;
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}
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void ARM_Dynarmic::SetTlsAddress(u64 address) {
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cb->tpidrro_el0 = address;
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}
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u64 ARM_Dynarmic::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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}
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void ARM_Dynarmic::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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}
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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ctx.pc = jit->GetPC();
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ctx.cpsr = jit->GetPstate();
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ctx.fpu_registers = jit->GetVectors();
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ctx.fpscr = jit->GetFpcr();
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}
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void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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jit->SetRegisters(ctx.cpu_registers);
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jit->SetSP(ctx.sp);
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jit->SetPC(ctx.pc);
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jit->SetPstate(static_cast<u32>(ctx.cpsr));
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jit->SetVectors(ctx.fpu_registers);
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jit->SetFpcr(static_cast<u32>(ctx.fpscr));
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}
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void ARM_Dynarmic::PrepareReschedule() {
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if (jit->IsExecuting()) {
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jit->HaltExecution();
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}
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}
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void ARM_Dynarmic::ClearInstructionCache() {
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jit->ClearCache();
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}
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void ARM_Dynarmic::ClearExclusiveState() {
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jit->ClearExclusiveState();
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}
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void ARM_Dynarmic::PageTableChanged() {
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jit = MakeJit();
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current_page_table = Memory::GetCurrentPageTable();
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}
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DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(size_t core_count) : monitor(core_count) {}
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DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
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void DynarmicExclusiveMonitor::SetExclusive(size_t core_index, u64 addr) {
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// Size doesn't actually matter.
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monitor.Mark(core_index, addr, 16);
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}
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void DynarmicExclusiveMonitor::ClearExclusive() {
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monitor.Clear();
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(size_t core_index, u64 vaddr, u8 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 1,
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[&] { Memory::Write8(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(size_t core_index, u64 vaddr, u16 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 2,
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[&] { Memory::Write16(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(size_t core_index, u64 vaddr, u32 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 4,
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[&] { Memory::Write32(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(size_t core_index, u64 vaddr, u64 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 8,
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[&] { Memory::Write64(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(size_t core_index, u64 vaddr,
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std::array<std::uint64_t, 2> value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 16, [&] {
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Memory::Write64(vaddr, value[0]);
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Memory::Write64(vaddr, value[1]);
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});
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}
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