150 lines
6.1 KiB
C++
150 lines
6.1 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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MaxwellDMA::MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager} {}
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void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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"Invalid MaxwellDMA register, increase the size of the Regs structure");
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regs.reg_array[method_call.method] = method_call.argument;
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#define MAXWELLDMA_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::MaxwellDMA::Regs, field_name) / sizeof(u32))
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switch (method_call.method) {
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case MAXWELLDMA_REG_INDEX(exec): {
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HandleCopy();
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break;
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}
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}
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#undef MAXWELLDMA_REG_INDEX
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}
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void MaxwellDMA::HandleCopy() {
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LOG_WARNING(HW_GPU, "Requested a DMA copy");
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const GPUVAddr source = regs.src_address.Address();
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const GPUVAddr dest = regs.dst_address.Address();
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// TODO(Subv): Perform more research and implement all features of this engine.
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ASSERT(regs.exec.enable_swizzle == 0);
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ASSERT(regs.exec.query_mode == Regs::QueryMode::None);
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ASSERT(regs.exec.query_intr == Regs::QueryIntr::None);
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ASSERT(regs.exec.copy_mode == Regs::CopyMode::Unk2);
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ASSERT(regs.dst_params.pos_x == 0);
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ASSERT(regs.dst_params.pos_y == 0);
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if (!regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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// If both the source and the destination are in block layout, assert.
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UNREACHABLE_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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// y_count).
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if (!regs.exec.enable_2d) {
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memory_manager.CopyBlock(dest, source, regs.x_count);
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return;
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}
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// If both the source and the destination are in linear layout, perform a line-by-line
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// copy. We're going to take a subrect of size (x_count, y_count) from the source
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// rectangle. There is no need to manually flush/invalidate the regions because
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// CopyBlock does that for us.
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for (u32 line = 0; line < regs.y_count; ++line) {
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const GPUVAddr source_line = source + line * regs.src_pitch;
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const GPUVAddr dest_line = dest + line * regs.dst_pitch;
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memory_manager.CopyBlock(dest_line, source_line, regs.x_count);
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}
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return;
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}
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ASSERT(regs.exec.enable_2d == 1);
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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ASSERT(regs.src_params.size_z == 1);
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
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const std::size_t src_size = Texture::CalculateSize(
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true, src_bytes_per_pixel, regs.src_params.size_x, regs.src_params.size_y,
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regs.src_params.size_z, regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
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const std::size_t dst_size = regs.dst_pitch * regs.y_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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memory_manager.ReadBlock(source, read_buffer.data(), src_size);
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memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
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Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
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regs.src_params.size_x, src_bytes_per_pixel, read_buffer.data(),
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write_buffer.data(), regs.src_params.BlockHeight(),
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regs.src_params.pos_x, regs.src_params.pos_y);
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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} else {
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ASSERT(regs.dst_params.BlockDepth() == 1);
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count;
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const std::size_t dst_size = Texture::CalculateSize(
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true, src_bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y,
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regs.dst_params.size_z, regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
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const std::size_t dst_layer_size = Texture::CalculateSize(
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true, src_bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y, 1,
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regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
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const std::size_t src_size = regs.src_pitch * regs.y_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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memory_manager.ReadBlock(source, read_buffer.data(), src_size);
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memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::SwizzleSubrect(regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x,
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src_bytes_per_pixel,
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write_buffer.data() + dst_layer_size * regs.dst_params.pos_z,
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read_buffer.data(), regs.dst_params.BlockHeight());
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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}
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}
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} // namespace Tegra::Engines
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