d57333406d
Long queries write a 128-bit result value to memory, which consists of a 64 bit query value and a 64 bit timestamp. In this implementation, only select=Zero of the Crop unit is implemented, this writes the query sequence as a 64 bit value, and a 0u64 value for the timestamp, since we emulate an infinitely fast GPU. This specific type was hwtested, but more rigorous tests should be performed in the future for the other types.
385 lines
15 KiB
C++
385 lines
15 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include "common/assert.h"
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#include "core/core.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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#include "video_core/textures/texture.h"
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#include "video_core/video_core.h"
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namespace Tegra {
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namespace Engines {
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager)
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: memory_manager(memory_manager), macro_interpreter(*this) {}
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void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
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auto macro_code = uploaded_macros.find(method);
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// The requested macro must have been uploaded already.
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ASSERT_MSG(macro_code != uploaded_macros.end(), "Macro %08X was not uploaded", method);
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// Reset the current macro and execute it.
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executing_macro = 0;
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macro_interpreter.Execute(macro_code->second, std::move(parameters));
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}
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void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
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// It is an error to write to a register other than the current macro's ARG register before it
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// has finished execution.
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if (executing_macro != 0) {
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ASSERT(method == executing_macro + 1);
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}
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// Methods after 0xE00 are special, they're actually triggers for some microcode that was
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// uploaded to the GPU during initialization.
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if (method >= MacroRegistersStart) {
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// We're trying to execute a macro
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if (executing_macro == 0) {
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// A macro call must begin by writing the macro method's register, not its argument.
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ASSERT_MSG((method % 2) == 0,
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"Can't start macro execution by writing to the ARGS register");
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executing_macro = method;
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}
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macro_params.push_back(value);
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// Call the macro when there are no more parameters in the command buffer
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if (remaining_params == 0) {
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CallMacroMethod(executing_macro, std::move(macro_params));
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}
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return;
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}
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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if (debug_context) {
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debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandLoaded, nullptr);
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}
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regs.reg_array[method] = value;
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switch (method) {
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case MAXWELL3D_REG_INDEX(macros.data): {
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ProcessMacroUpload(value);
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break;
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}
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case MAXWELL3D_REG_INDEX(code_address.code_address_high):
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case MAXWELL3D_REG_INDEX(code_address.code_address_low): {
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// Note: For some reason games (like Puyo Puyo Tetris) seem to write 0 to the CODE_ADDRESS
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// register, we do not currently know if that's intended or a bug, so we assert it lest
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// stuff breaks in other places (like the shader address calculation).
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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}
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[0]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[1]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[2]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[3]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[4]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[5]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[6]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[7]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[8]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[9]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[10]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[11]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[12]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[13]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[14]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[15]): {
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ProcessCBData(value);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Vertex);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[1].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationControl);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[2].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationEval);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[3].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Geometry);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[4].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Fragment);
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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break;
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}
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case MAXWELL3D_REG_INDEX(query.query_get): {
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ProcessQueryGet();
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break;
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}
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default:
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break;
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}
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VideoCore::g_renderer->Rasterizer()->NotifyMaxwellRegisterChanged(method);
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if (debug_context) {
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debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandProcessed, nullptr);
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}
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}
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void Maxwell3D::ProcessMacroUpload(u32 data) {
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// Store the uploaded macro code to interpret them when they're called.
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auto& macro = uploaded_macros[regs.macros.entry * 2 + MacroRegistersStart];
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macro.push_back(data);
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}
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void Maxwell3D::ProcessQueryGet() {
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GPUVAddr sequence_address = regs.query.QueryAddress();
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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// VAddr before writing.
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boost::optional<VAddr> address = memory_manager.GpuToCpuAddress(sequence_address);
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// TODO(Subv): Support the other query units.
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ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
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"Units other than CROP are unimplemented");
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u32 value = Memory::Read32(*address);
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u64 result = 0;
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// TODO(Subv): Support the other query variables
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switch (regs.query.query_get.select) {
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case Regs::QuerySelect::Zero:
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// This seems to actually write the query sequence to the query address.
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result = regs.query.query_sequence;
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented query select type {}",
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static_cast<u32>(regs.query.query_get.select.Value()));
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}
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// TODO(Subv): Research and implement how query sync conditions work.
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struct LongQueryResult {
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u64_le value;
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u64_le timestamp;
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};
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static_assert(sizeof(LongQueryResult) == 16, "LongQueryResult has wrong size");
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switch (regs.query.query_get.mode) {
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case Regs::QueryMode::Write:
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case Regs::QueryMode::Write2: {
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u32 sequence = regs.query.query_sequence;
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if (regs.query.query_get.short_query) {
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// Write the current query sequence to the sequence address.
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// TODO(Subv): Find out what happens if you use a long query type but mark it as a short
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// query.
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Memory::Write32(*address, sequence);
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} else {
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// Write the 128-bit result structure in long mode. Note: We emulate an infinitely fast
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// GPU, this command may actually take a while to complete in real hardware due to GPU
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// wait queues.
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LongQueryResult query_result{};
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query_result.value = result;
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// TODO(Subv): Generate a real GPU timestamp and write it here instead of 0
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query_result.timestamp = 0;
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Memory::WriteBlock(*address, &query_result, sizeof(query_result));
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Query mode {} not implemented",
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static_cast<u32>(regs.query.query_get.mode.Value()));
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}
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}
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void Maxwell3D::DrawArrays() {
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NGLOG_DEBUG(HW_GPU, "called, topology={}, count={}",
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static_cast<u32>(regs.draw.topology.Value()), regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_array.count && regs.vertex_buffer.count), "Both indexed and direct?");
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auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
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if (debug_context) {
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debug_context->OnEvent(Tegra::DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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}
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if (debug_context) {
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debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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const bool is_indexed{regs.index_array.count && !regs.vertex_buffer.count};
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(is_indexed);
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// TODO(bunnei): Below, we reset vertex count so that we can use these registers to determine if
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// the game is trying to draw indexed or direct mode. This needs to be verified on HW still -
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// it's possible that it is incorrect and that there is some other register used to specify the
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// drawing mode.
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if (is_indexed) {
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regs.index_array.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& bind_data = regs.cb_bind[static_cast<size_t>(stage)];
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auto& buffer = shader.const_buffers[bind_data.index];
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buffer.enabled = bind_data.valid.Value() != 0;
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buffer.index = bind_data.index;
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buffer.address = regs.const_buffer.BufferAddress();
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buffer.size = regs.const_buffer.cb_size;
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}
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void Maxwell3D::ProcessCBData(u32 value) {
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// Write the input value to the current const buffer at the current position.
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GPUVAddr buffer_address = regs.const_buffer.BufferAddress();
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ASSERT(buffer_address != 0);
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// Don't allow writing past the end of the buffer.
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ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
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boost::optional<VAddr> address =
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memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
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Memory::Write32(*address, value);
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// Increment the current buffer position.
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
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boost::optional<VAddr> tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(*tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear ||
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tic_entry.header_version == Texture::TICHeaderVersion::Pitch,
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"TIC versions other than BlockLinear or Pitch are unimplemented");
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ASSERT_MSG((tic_entry.texture_type == Texture::TextureType::Texture2D) ||
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(tic_entry.texture_type == Texture::TextureType::Texture2DNoMipmap),
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"Texture types other than Texture2D are unimplemented");
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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// TODO(Subv): Only UNORM formats are supported for now.
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ASSERT(r_type == Texture::ComponentType::UNORM);
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return tic_entry;
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}
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Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
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GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
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GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
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boost::optional<VAddr> tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
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Texture::TSCEntry tsc_entry;
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Memory::ReadBlock(*tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
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return tsc_entry;
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}
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std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) const {
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std::vector<Texture::FullTextureInfo> textures;
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auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tex_info_buffer_end = tex_info_buffer.address + tex_info_buffer.size;
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// Offset into the texture constbuffer where the texture info begins.
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static constexpr size_t TextureInfoOffset = 0x20;
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for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
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current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
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Texture::TextureHandle tex_handle{
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Memory::Read32(*memory_manager.GpuToCpuAddress(current_texture))};
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Texture::FullTextureInfo tex_info{};
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// TODO(Subv): Use the shader to determine which textures are actually accessed.
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tex_info.index = (current_texture - tex_info_buffer.address - TextureInfoOffset) /
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sizeof(Texture::TextureHandle);
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// Load the TIC data.
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if (tex_handle.tic_id != 0) {
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tex_info.enabled = true;
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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}
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// Load the TSC data
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if (tex_handle.tsc_id != 0) {
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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}
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if (tex_info.enabled)
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textures.push_back(tex_info);
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}
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return textures;
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}
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u32 Maxwell3D::GetRegisterValue(u32 method) const {
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ASSERT_MSG(method < Regs::NUM_REGS, "Invalid Maxwell3D register");
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return regs.reg_array[method];
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}
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bool Maxwell3D::IsShaderStageEnabled(Regs::ShaderStage stage) const {
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// The Vertex stage is always enabled.
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if (stage == Regs::ShaderStage::Vertex)
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return true;
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switch (stage) {
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case Regs::ShaderStage::TesselationControl:
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return regs.shader_config[static_cast<size_t>(Regs::ShaderProgram::TesselationControl)]
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.enable != 0;
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case Regs::ShaderStage::TesselationEval:
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return regs.shader_config[static_cast<size_t>(Regs::ShaderProgram::TesselationEval)]
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.enable != 0;
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case Regs::ShaderStage::Geometry:
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return regs.shader_config[static_cast<size_t>(Regs::ShaderProgram::Geometry)].enable != 0;
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case Regs::ShaderStage::Fragment:
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return regs.shader_config[static_cast<size_t>(Regs::ShaderProgram::Fragment)].enable != 0;
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}
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UNREACHABLE();
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}
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} // namespace Engines
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} // namespace Tegra
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