590 lines
19 KiB
C++
590 lines
19 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <unordered_map>
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#include <vector>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/math_util.h"
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#include "video_core/gpu.h"
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#include "video_core/macro_interpreter.h"
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#include "video_core/memory_manager.h"
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#include "video_core/textures/texture.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D final {
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public:
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explicit Maxwell3D(MemoryManager& memory_manager);
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~Maxwell3D() = default;
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NumRenderTargets = 8;
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static constexpr size_t NumViewports = 16;
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static constexpr size_t NumCBData = 16;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t NumVertexAttributes = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderStage = 5;
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// Maximum number of const buffers per shader stage.
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static constexpr size_t MaxConstBuffers = 16;
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enum class QueryMode : u32 {
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Write = 0,
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Sync = 1,
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};
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enum class ShaderProgram : u32 {
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VertexA = 0,
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VertexB = 1,
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TesselationControl = 2,
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TesselationEval = 3,
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Geometry = 4,
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Fragment = 5,
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};
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enum class ShaderStage : u32 {
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Vertex = 0,
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TesselationControl = 1,
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TesselationEval = 2,
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Geometry = 3,
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Fragment = 4,
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};
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struct VertexAttribute {
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enum class Size : u32 {
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Size_32_32_32_32 = 0x01,
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Size_32_32_32 = 0x02,
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Size_16_16_16_16 = 0x03,
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Size_32_32 = 0x04,
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Size_16_16_16 = 0x05,
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Size_8_8_8_8 = 0x0a,
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Size_16_16 = 0x0f,
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Size_32 = 0x12,
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Size_8_8_8 = 0x13,
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Size_8_8 = 0x18,
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Size_16 = 0x1b,
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Size_8 = 0x1d,
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Size_10_10_10_2 = 0x30,
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Size_11_11_10 = 0x31,
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};
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enum class Type : u32 {
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SignedNorm = 1,
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UnsignedNorm = 2,
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SignedInt = 3,
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UnsignedInt = 4,
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UnsignedScaled = 5,
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SignedScaled = 6,
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Float = 7,
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};
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union {
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BitField<0, 5, u32> buffer;
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BitField<6, 1, u32> constant;
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BitField<7, 14, u32> offset;
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BitField<21, 6, Size> size;
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BitField<27, 3, Type> type;
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BitField<31, 1, u32> bgra;
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};
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u32 ComponentCount() const {
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switch (size) {
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case Size::Size_32_32_32_32:
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return 4;
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case Size::Size_32_32_32:
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return 3;
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case Size::Size_16_16_16_16:
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return 4;
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case Size::Size_32_32:
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return 2;
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case Size::Size_16_16_16:
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return 3;
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case Size::Size_8_8_8_8:
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return 4;
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case Size::Size_16_16:
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return 2;
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case Size::Size_32:
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return 1;
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case Size::Size_8_8_8:
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return 3;
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case Size::Size_8_8:
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return 2;
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case Size::Size_16:
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return 1;
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case Size::Size_8:
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return 1;
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case Size::Size_10_10_10_2:
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return 4;
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case Size::Size_11_11_10:
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return 3;
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default:
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UNREACHABLE();
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}
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}
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u32 SizeInBytes() const {
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switch (size) {
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case Size::Size_32_32_32_32:
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return 16;
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case Size::Size_32_32_32:
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return 12;
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case Size::Size_16_16_16_16:
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return 8;
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case Size::Size_32_32:
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return 8;
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case Size::Size_16_16_16:
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return 6;
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case Size::Size_8_8_8_8:
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return 4;
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case Size::Size_16_16:
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return 4;
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case Size::Size_32:
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return 4;
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case Size::Size_8_8_8:
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return 3;
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case Size::Size_8_8:
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return 2;
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case Size::Size_16:
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return 2;
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case Size::Size_8:
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return 1;
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case Size::Size_10_10_10_2:
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return 4;
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case Size::Size_11_11_10:
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return 4;
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default:
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UNREACHABLE();
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}
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}
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std::string SizeString() const {
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switch (size) {
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case Size::Size_32_32_32_32:
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return "32_32_32_32";
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case Size::Size_32_32_32:
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return "32_32_32";
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case Size::Size_16_16_16_16:
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return "16_16_16_16";
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case Size::Size_32_32:
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return "32_32";
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case Size::Size_16_16_16:
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return "16_16_16";
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case Size::Size_8_8_8_8:
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return "8_8_8_8";
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case Size::Size_16_16:
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return "16_16";
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case Size::Size_32:
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return "32";
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case Size::Size_8_8_8:
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return "8_8_8";
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case Size::Size_8_8:
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return "8_8";
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case Size::Size_16:
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return "16";
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case Size::Size_8:
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return "8";
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case Size::Size_10_10_10_2:
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return "10_10_10_2";
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case Size::Size_11_11_10:
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return "11_11_10";
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}
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UNREACHABLE();
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return {};
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}
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std::string TypeString() const {
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switch (type) {
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case Type::SignedNorm:
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return "SNORM";
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case Type::UnsignedNorm:
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return "UNORM";
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case Type::SignedInt:
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return "SINT";
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case Type::UnsignedInt:
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return "UINT";
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case Type::UnsignedScaled:
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return "USCALED";
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case Type::SignedScaled:
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return "SSCALED";
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case Type::Float:
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return "FLOAT";
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}
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UNREACHABLE();
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return {};
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}
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bool IsNormalized() const {
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return (type == Type::SignedNorm) || (type == Type::UnsignedNorm);
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}
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};
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enum class PrimitiveTopology : u32 {
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Points = 0x0,
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Lines = 0x1,
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LineLoop = 0x2,
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LineStrip = 0x3,
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Triangles = 0x4,
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TriangleStrip = 0x5,
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TriangleFan = 0x6,
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Quads = 0x7,
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QuadStrip = 0x8,
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Polygon = 0x9,
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LinesAdjacency = 0xa,
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LineStripAdjacency = 0xb,
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TrianglesAdjacency = 0xc,
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TriangleStripAdjacency = 0xd,
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Patches = 0xe,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x200);
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struct {
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u32 address_high;
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u32 address_low;
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u32 width;
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u32 height;
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Tegra::RenderTargetFormat format;
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u32 block_dimensions;
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u32 array_mode;
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u32 layer_stride;
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u32 base_layer;
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INSERT_PADDING_WORDS(7);
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} rt[NumRenderTargets];
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INSERT_PADDING_WORDS(0x80);
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struct {
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union {
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BitField<0, 16, u32> x;
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BitField<16, 16, u32> width;
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};
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union {
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BitField<0, 16, u32> y;
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BitField<16, 16, u32> height;
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};
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float depth_range_near;
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float depth_range_far;
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MathUtil::Rectangle<s32> GetRect() const {
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return {
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static_cast<s32>(x), // left
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static_cast<s32>(y + height), // top
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static_cast<s32>(x + width), // right
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static_cast<s32>(y) // bottom
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};
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};
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} viewport[NumViewports];
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INSERT_PADDING_WORDS(0x1D);
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struct {
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u32 first;
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u32 count;
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} vertex_buffer;
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INSERT_PADDING_WORDS(0x99);
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struct {
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u32 address_high;
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u32 address_low;
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u32 format;
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u32 block_dimensions;
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u32 layer_stride;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} zeta;
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INSERT_PADDING_WORDS(0x5B);
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VertexAttribute vertex_attrib_format[NumVertexAttributes];
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INSERT_PADDING_WORDS(0xF);
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struct {
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union {
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BitField<0, 4, u32> count;
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};
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} rt_control;
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INSERT_PADDING_WORDS(0xCF);
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struct {
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u32 tsc_address_high;
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u32 tsc_address_low;
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u32 tsc_limit;
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GPUVAddr TSCAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(tsc_address_high) << 32) | tsc_address_low);
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}
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} tsc;
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INSERT_PADDING_WORDS(0x3);
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struct {
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u32 tic_address_high;
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u32 tic_address_low;
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u32 tic_limit;
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GPUVAddr TICAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(tic_address_high) << 32) | tic_address_low);
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}
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} tic;
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INSERT_PADDING_WORDS(0x22);
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struct {
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u32 code_address_high;
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u32 code_address_low;
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GPUVAddr CodeAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(code_address_high) << 32) | code_address_low);
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}
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} code_address;
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INSERT_PADDING_WORDS(1);
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struct {
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u32 vertex_end_gl;
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union {
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u32 vertex_begin_gl;
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BitField<0, 16, PrimitiveTopology> topology;
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};
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} draw;
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INSERT_PADDING_WORDS(0x139);
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struct {
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u32 query_address_high;
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u32 query_address_low;
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u32 query_sequence;
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union {
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u32 raw;
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BitField<0, 2, QueryMode> mode;
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BitField<4, 1, u32> fence;
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BitField<12, 4, u32> unit;
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} query_get;
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GPUVAddr QueryAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(query_address_high) << 32) | query_address_low);
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}
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} query;
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INSERT_PADDING_WORDS(0x3C);
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struct {
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union {
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BitField<0, 12, u32> stride;
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BitField<12, 1, u32> enable;
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};
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u32 start_high;
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u32 start_low;
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u32 divisor;
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GPUVAddr StartAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(start_high) << 32) |
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start_low);
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}
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} vertex_array[NumVertexArrays];
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INSERT_PADDING_WORDS(0x40);
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struct {
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u32 limit_high;
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u32 limit_low;
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GPUVAddr LimitAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(limit_high) << 32) |
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limit_low);
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}
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} vertex_array_limit[NumVertexArrays];
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struct {
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union {
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BitField<0, 1, u32> enable;
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BitField<4, 4, ShaderProgram> program;
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};
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u32 offset;
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INSERT_PADDING_WORDS(14);
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} shader_config[MaxShaderProgram];
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INSERT_PADDING_WORDS(0x80);
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struct {
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u32 cb_size;
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u32 cb_address_high;
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(cb_address_high) << 32) | cb_address_low);
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}
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} const_buffer;
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INSERT_PADDING_WORDS(0x10);
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struct {
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union {
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u32 raw_config;
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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};
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INSERT_PADDING_WORDS(7);
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} cb_bind[MaxShaderStage];
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INSERT_PADDING_WORDS(0x56);
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u32 tex_cb_index;
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INSERT_PADDING_WORDS(0x395);
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struct {
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/// Compressed address of a buffer that holds information about bound SSBOs.
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/// This address is usually bound to c0 in the shaders.
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u32 buffer_address;
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(buffer_address) << 8;
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}
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} ssbo_info;
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INSERT_PADDING_WORDS(0x11);
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struct {
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u32 address[MaxShaderStage];
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u32 size[MaxShaderStage];
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} tex_info_buffers;
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INSERT_PADDING_WORDS(0x102);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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struct State {
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struct ConstBufferInfo {
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GPUVAddr address;
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u32 index;
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u32 size;
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bool enabled;
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};
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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std::array<ShaderStageInfo, Regs::MaxShaderStage> shader_stages;
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};
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State state{};
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MemoryManager& memory_manager;
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/// Reads a register value located at the input method address
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u32 GetRegisterValue(u32 method) const;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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/// Uploads the code for a GPU macro program associated with the specified entry.
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Returns a list of enabled textures for the specified shader stage.
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std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
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/// Returns whether the specified shader stage is enabled or not.
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bool IsShaderStageEnabled(Regs::ShaderStage stage) const;
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private:
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std::unordered_map<u32, std::vector<u32>> uploaded_macros;
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/// Macro method that is currently being executed / being fed parameters.
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u32 executing_macro = 0;
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/// Parameters that have been submitted to the macro call so far.
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std::vector<u32> macro_params;
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/// Interpreter for the macro codes uploaded to the GPU.
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MacroInterpreter macro_interpreter;
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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/**
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* Call a macro on this engine.
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMacroMethod(u32 method, std::vector<u32> parameters);
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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/// Handles a write to the CB_DATA[i] register.
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void ProcessCBData(u32 value);
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderStage stage);
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(viewport, 0x300);
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ASSERT_REG_POSITION(vertex_buffer, 0x35D);
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ASSERT_REG_POSITION(zeta, 0x3F8);
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ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
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ASSERT_REG_POSITION(rt_control, 0x487);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(ssbo_info, 0xD18);
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ASSERT_REG_POSITION(tex_info_buffers.address[0], 0xD2A);
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ASSERT_REG_POSITION(tex_info_buffers.size[0], 0xD2F);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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