77 lines
2.3 KiB
C++
77 lines
2.3 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D final {
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public:
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explicit Maxwell3D(MemoryManager& memory_manager);
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~Maxwell3D() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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enum class QueryMode : u32 {
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Write = 0,
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Sync = 1,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x6C0);
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struct {
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u32 query_address_high;
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u32 query_address_low;
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u32 query_sequence;
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union {
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u32 raw;
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BitField<0, 2, QueryMode> mode;
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BitField<4, 1, u32> fence;
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BitField<12, 4, u32> unit;
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} query_get;
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GPUVAddr QueryAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(query_address_high) << 32) | query_address_low);
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}
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} query;
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INSERT_PADDING_WORDS(0x772);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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private:
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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MemoryManager& memory_manager;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(query, 0x6C0);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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