120 lines
3.4 KiB
C++
120 lines
3.4 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <string>
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#include <string_view>
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#include <fmt/format.h>
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#include "shader_recompiler/backend/glsl/reg_alloc.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#pragma optimize("", off)
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namespace Shader::Backend::GLSL {
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namespace {
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constexpr std::string_view SWIZZLE = "xyzw";
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std::string Representation(Id id) {
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if (id.is_condition_code != 0) {
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throw NotImplementedException("Condition code");
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}
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if (id.is_spill != 0) {
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throw NotImplementedException("Spilling");
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}
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const u32 num_elements{id.num_elements_minus_one + 1};
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const u32 index{static_cast<u32>(id.index)};
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return fmt::format("R{}", index);
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}
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std::string MakeImm(const IR::Value& value) {
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switch (value.Type()) {
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case IR::Type::U1:
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return fmt::format("{}", value.U1() ? "true" : "false");
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case IR::Type::U32:
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return fmt::format("{}", value.U32());
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case IR::Type::F32:
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return fmt::format("{}", value.F32());
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case IR::Type::U64:
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return fmt::format("{}", value.U64());
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case IR::Type::F64:
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return fmt::format("{}", value.F64());
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default:
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throw NotImplementedException("Immediate type {}", value.Type());
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}
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}
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} // Anonymous namespace
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std::string RegAlloc::Define(IR::Inst& inst, u32 num_elements, u32 alignment) {
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const Id id{Alloc(num_elements, alignment)};
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inst.SetDefinition<Id>(id);
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return Representation(id);
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}
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std::string RegAlloc::Consume(const IR::Value& value) {
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const auto result = value.IsImmediate() ? MakeImm(value) : Consume(*value.InstRecursive());
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return result;
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}
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std::string RegAlloc::Consume(IR::Inst& inst) {
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const Id id{inst.Definition<Id>()};
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inst.DestructiveRemoveUsage();
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if (!inst.HasUses()) {
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Free(id);
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}
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return Representation(inst.Definition<Id>());
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}
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Id RegAlloc::Alloc(u32 num_elements, [[maybe_unused]] u32 alignment) {
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for (size_t reg = 0; reg < NUM_REGS; ++reg) {
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if (register_use[reg]) {
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continue;
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}
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num_used_registers = std::max(num_used_registers, reg + 1);
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register_use[reg] = true;
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return Id{
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.base_element = 0,
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.num_elements_minus_one = num_elements - 1,
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.index = static_cast<u32>(reg),
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.is_spill = 0,
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.is_condition_code = 0,
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};
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}
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throw NotImplementedException("Register spilling");
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}
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void RegAlloc::Free(Id id) {
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if (id.is_spill != 0) {
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throw NotImplementedException("Free spill");
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}
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register_use[id.index] = false;
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}
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/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::Identity:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastU32F32:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::BitCastF32U32:
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case IR::Opcode::BitCastF64U64:
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return true;
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default:
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return false;
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}
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}
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/*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) {
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IR::Inst* it{&inst};
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while (IsAliased(*it)) {
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const IR::Value arg{it->Arg(0)};
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if (arg.IsImmediate()) {
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break;
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}
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it = arg.InstRecursive();
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}
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return *it;
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}
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} // namespace Shader::Backend::GLSL
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