102 lines
4.0 KiB
C++
102 lines
4.0 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::ConditionCode;
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u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::EXIT: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}",
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static_cast<u32>(cc));
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switch (instr.flow.cond) {
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case Tegra::Shader::FlowCondition::Always:
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bb.push_back(Operation(OperationCode::Exit));
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if (instr.pred.pred_index == static_cast<u64>(Tegra::Shader::Pred::UnusedIndex)) {
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// If this is an unconditional exit then just end processing here,
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// otherwise we have to account for the possibility of the condition
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// not being met, so continue processing the next instruction.
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pc = MAX_PROGRAM_LENGTH - 1;
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}
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break;
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case Tegra::Shader::FlowCondition::Fcsm_Tr:
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// TODO(bunnei): What is this used for? If we assume this conditon is not
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// satisifed, dual vertex shaders in Farming Simulator make more sense
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UNIMPLEMENTED_MSG("Skipping unknown FlowCondition::Fcsm_Tr");
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break;
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default:
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UNIMPLEMENTED_MSG("Unhandled flow condition: {}",
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static_cast<u32>(instr.flow.cond.Value()));
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}
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break;
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}
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case OpCode::Id::BRA: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"BRA with constant buffers are not implemented");
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF(cc != Tegra::Shader::ConditionCode::T);
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const u32 target = pc + instr.bra.GetBranchTarget();
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bb.push_back(Operation(OperationCode::Bra, Immediate(target)));
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break;
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}
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case OpCode::Id::SSY: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer flow is not supported");
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// The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the
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// target of the jump that the SYNC instruction will make. The SSY opcode has a similar
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// structure to the BRA opcode.
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bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget())));
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break;
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}
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case OpCode::Id::SYNC: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}",
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static_cast<u32>(cc));
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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bb.push_back(Operation(OperationCode::Sync));
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break;
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}
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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instr.ipa.sample_mode.Value()};
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const Node input_attr = GetInputAttribute(attribute.index, attribute.element, input_mode);
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const Node ipa = Operation(OperationCode::Ipa, input_attr);
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const Node value = GetSaturatedFloat(ipa, instr.ipa.saturate);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::DEPBAR: {
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LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed");
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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