162d641a30
- Swizzlers now return const objects so that things like "first_vec4.xyz() = some_vec3" now will fail to compile (ideally we should support some vector holding references to make this actually work). - The methods "InsertBeforeX/Y/Z" and "Append" have been replaced by more versions of MakeVec, which now also supports building new vectors from vectors. - Vector library now follows C++ type promotion rules (hence, the result of Vec2<u8> with another Vec2<u8> is now a Vec2<int>).
285 lines
8.0 KiB
C++
285 lines
8.0 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include <initializer_list>
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#include <common/common_types.h>
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#include "math.h"
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#include "pica.h"
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namespace Pica {
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namespace VertexShader {
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struct InputVertex {
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Math::Vec4<float24> attr[16];
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};
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struct OutputVertex {
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OutputVertex() = default;
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// VS output attributes
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Math::Vec4<float24> pos;
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Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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// Padding for optimal alignment
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float24 pad[14];
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// Attributes used to store intermediate results
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// position after perspective divide
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Math::Vec3<float24> screenpos;
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float24 pad2;
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// Linear interpolation
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// factor: 0=this, 1=vtx
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void Lerp(float24 factor, const OutputVertex& vtx) {
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pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
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// TODO: Should perform perspective correct interpolation here...
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tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
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screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
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color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
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}
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// Linear interpolation
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// factor: 0=v0, 1=v1
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static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
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OutputVertex ret = v0;
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ret.Lerp(factor, v1);
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return ret;
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}
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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union Instruction {
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enum class OpCode : u32 {
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ADD = 0x0,
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DP3 = 0x1,
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DP4 = 0x2,
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MUL = 0x8,
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MAX = 0xC,
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MIN = 0xD,
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RCP = 0xE,
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RSQ = 0xF,
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MOV = 0x13,
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RET = 0x21,
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FLS = 0x22, // Flush
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CALL = 0x24,
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};
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std::string GetOpCodeName() const {
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std::map<OpCode, std::string> map = {
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{ OpCode::ADD, "ADD" },
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{ OpCode::DP3, "DP3" },
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{ OpCode::DP4, "DP4" },
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{ OpCode::MUL, "MUL" },
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{ OpCode::MAX, "MAX" },
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{ OpCode::MIN, "MIN" },
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{ OpCode::RCP, "RCP" },
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{ OpCode::RSQ, "RSQ" },
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{ OpCode::MOV, "MOV" },
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{ OpCode::RET, "RET" },
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{ OpCode::FLS, "FLS" },
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};
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auto it = map.find(opcode);
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if (it == map.end())
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return "UNK";
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else
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return it->second;
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}
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u32 hex;
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BitField<0x1a, 0x6, OpCode> opcode;
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// General notes:
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//
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// When two input registers are used, one of them uses a 5-bit index while the other
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// one uses a 7-bit index. This is because at most one floating point uniform may be used
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// as an input.
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// Format used e.g. by arithmetic instructions and comparisons
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// "src1" and "src2" specify register indices (i.e. indices referring to groups of 4 floats),
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// while "dest" addresses individual floats.
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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template<class BitFieldType>
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struct SourceRegister : BitFieldType {
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enum RegisterType {
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Input,
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Temporary,
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FloatUniform
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};
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RegisterType GetRegisterType() const {
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if (BitFieldType::Value() < 0x10)
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return Input;
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else if (BitFieldType::Value() < 0x20)
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return Temporary;
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else
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return FloatUniform;
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}
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int GetIndex() const {
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if (GetRegisterType() == Input)
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return BitFieldType::Value();
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else if (GetRegisterType() == Temporary)
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return BitFieldType::Value() - 0x10;
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else if (GetRegisterType() == FloatUniform)
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return BitFieldType::Value() - 0x20;
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Input, "i" },
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{ Temporary, "t" },
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{ FloatUniform, "f" },
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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};
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SourceRegister<BitField<0x07, 0x5, u32>> src2;
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SourceRegister<BitField<0x0c, 0x7, u32>> src1;
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struct : BitField<0x15, 0x5, u32>
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{
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enum RegisterType {
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Output,
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Temporary,
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Unknown
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};
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RegisterType GetRegisterType() const {
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if (Value() < 0x8)
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return Output;
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else if (Value() < 0x10)
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return Unknown;
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else
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return Temporary;
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}
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int GetIndex() const {
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if (GetRegisterType() == Output)
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return Value();
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else if (GetRegisterType() == Temporary)
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return Value() - 0x10;
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else
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return Value();
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Output, "o" },
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{ Temporary, "t" },
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{ Unknown, "u" }
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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} dest;
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} common;
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// Format used for flow control instructions ("if")
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union {
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BitField<0x00, 0x8, u32> num_instructions;
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BitField<0x0a, 0xc, u32> offset_words;
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} flow_control;
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};
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static_assert(std::is_standard_layout<Instruction>::value, "Structure is not using standard layout!");
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union SwizzlePattern {
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u32 hex;
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enum class Selector : u32 {
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x = 0,
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y = 1,
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z = 2,
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w = 3
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};
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Selector GetSelectorSrc1(int comp) const {
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Selector selectors[] = {
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src1_selector_0, src1_selector_1, src1_selector_2, src1_selector_3
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};
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return selectors[comp];
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}
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Selector GetSelectorSrc2(int comp) const {
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Selector selectors[] = {
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src2_selector_0, src2_selector_1, src2_selector_2, src2_selector_3
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};
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return selectors[comp];
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}
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bool DestComponentEnabled(int i) const {
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return (dest_mask & (0x8 >> i));
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}
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std::string SelectorToString(bool src2) const {
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std::map<Selector, std::string> map = {
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{ Selector::x, "x" },
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{ Selector::y, "y" },
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{ Selector::z, "z" },
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{ Selector::w, "w" }
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};
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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ret += map.at(src2 ? GetSelectorSrc2(i) : GetSelectorSrc1(i));
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}
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return ret;
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}
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std::string DestMaskToString() const {
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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if (!DestComponentEnabled(i))
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ret += "_";
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else
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ret += "xyzw"[i];
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}
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return ret;
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}
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// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
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BitField< 0, 4, u32> dest_mask;
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BitField< 4, 1, u32> negate; // negates src1
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BitField< 5, 2, Selector> src1_selector_3;
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BitField< 7, 2, Selector> src1_selector_2;
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BitField< 9, 2, Selector> src1_selector_1;
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BitField<11, 2, Selector> src1_selector_0;
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BitField<14, 2, Selector> src2_selector_3;
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BitField<16, 2, Selector> src2_selector_2;
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BitField<18, 2, Selector> src2_selector_1;
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BitField<20, 2, Selector> src2_selector_0;
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BitField<31, 1, u32> flag; // not sure what this means, maybe it's the sign?
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};
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void SubmitShaderMemoryChange(u32 addr, u32 value);
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void SubmitSwizzleDataChange(u32 addr, u32 value);
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OutputVertex RunShader(const InputVertex& input, int num_attributes);
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Math::Vec4<float24>& GetFloatUniform(u32 index);
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} // namespace
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} // namespace
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