2a9d17b7e7
Rename registers in the MaxwellDMA class to match Nvidia's official documentation. This one can be found here: https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h While we are at it, reorganize the code in MaxwellDMA to be separated in different functions.
273 lines
7.5 KiB
C++
273 lines
7.5 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_interface.h"
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#include "video_core/gpu.h"
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namespace Core {
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class System;
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}
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namespace Tegra {
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class MemoryManager;
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}
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namespace Tegra::Engines {
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/**
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* This engine is known as gk104_copy. Documentation can be found in:
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* https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h
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* https://github.com/envytools/envytools/blob/master/rnndb/fifo/gk104_copy.xml
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*/
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class MaxwellDMA final : public EngineInterface {
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public:
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struct PackedGPUVAddr {
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u32 upper;
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u32 lower;
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constexpr operator GPUVAddr() const noexcept {
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return (static_cast<GPUVAddr>(upper & 0xff) << 32) | lower;
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}
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};
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union BlockSize {
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BitField<0, 4, u32> width;
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BitField<4, 4, u32> height;
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BitField<8, 4, u32> depth;
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BitField<12, 4, u32> gob_height;
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};
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static_assert(sizeof(BlockSize) == 4);
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union Origin {
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BitField<0, 16, u32> x;
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BitField<16, 16, u32> y;
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};
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static_assert(sizeof(Origin) == 4);
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struct Parameters {
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BlockSize block_size;
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u32 width;
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u32 height;
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u32 depth;
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u32 layer;
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Origin origin;
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};
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static_assert(sizeof(Parameters) == 24);
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struct Semaphore {
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PackedGPUVAddr address;
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u32 payload;
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};
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static_assert(sizeof(Semaphore) == 12);
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struct RenderEnable {
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enum class Mode : u32 {
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FALSE = 0,
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TRUE = 1,
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CONDITIONAL = 2,
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RENDER_IF_EQUAL = 3,
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RENDER_IF_NOT_EQUAL = 4,
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};
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PackedGPUVAddr address;
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BitField<0, 3, Mode> mode;
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};
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static_assert(sizeof(RenderEnable) == 12);
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enum class PhysModeTarget : u32 {
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LOCAL_FB = 0,
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COHERENT_SYSMEM = 1,
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NONCOHERENT_SYSMEM = 2,
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};
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using PhysMode = BitField<0, 2, PhysModeTarget>;
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union LaunchDMA {
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enum class DataTransferType : u32 {
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NONE = 0,
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PIPELINED = 1,
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NON_PIPELINED = 2,
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};
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enum class SemaphoreType : u32 {
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NONE = 0,
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RELEASE_ONE_WORD_SEMAPHORE = 1,
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RELEASE_FOUR_WORD_SEMAPHORE = 2,
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};
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enum class InterruptType : u32 {
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NONE = 0,
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BLOCKING = 1,
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NON_BLOCKING = 2,
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};
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enum class MemoryLayout : u32 {
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BLOCKLINEAR = 0,
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PITCH = 1,
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};
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enum class Type : u32 {
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VIRTUAL = 0,
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PHYSICAL = 1,
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};
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enum class SemaphoreReduction : u32 {
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IMIN = 0,
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IMAX = 1,
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IXOR = 2,
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IAND = 3,
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IOR = 4,
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IADD = 5,
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INC = 6,
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DEC = 7,
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FADD = 0xA,
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};
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enum class SemaphoreReductionSign : u32 {
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SIGNED = 0,
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UNSIGNED = 1,
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};
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enum class BypassL2 : u32 {
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USE_PTE_SETTING = 0,
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FORCE_VOLATILE = 1,
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};
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BitField<0, 2, DataTransferType> data_transfer_type;
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BitField<2, 1, u32> flush_enable;
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BitField<3, 2, SemaphoreType> semaphore_type;
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BitField<5, 2, InterruptType> interrupt_type;
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BitField<7, 1, MemoryLayout> src_memory_layout;
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BitField<8, 1, MemoryLayout> dst_memory_layout;
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BitField<9, 1, u32> multi_line_enable;
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BitField<10, 1, u32> remap_enable;
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BitField<11, 1, u32> rmwdisable;
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BitField<12, 1, Type> src_type;
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BitField<13, 1, Type> dst_type;
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BitField<14, 4, SemaphoreReduction> semaphore_reduction;
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BitField<18, 1, SemaphoreReductionSign> semaphore_reduction_sign;
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BitField<19, 1, u32> reduction_enable;
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BitField<20, 1, BypassL2> bypass_l2;
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};
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static_assert(sizeof(LaunchDMA) == 4);
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struct RemapConst {
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enum Swizzle : u32 {
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SRC_X = 0,
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SRC_Y = 1,
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SRC_Z = 2,
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SRC_W = 3,
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CONST_A = 4,
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CONST_B = 5,
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NO_WRITE = 6,
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};
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PackedGPUVAddr address;
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union {
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BitField<0, 3, Swizzle> dst_x;
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BitField<4, 3, Swizzle> dst_y;
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BitField<8, 3, Swizzle> dst_z;
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BitField<12, 3, Swizzle> dst_w;
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BitField<16, 2, u32> component_size_minus_one;
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BitField<20, 2, u32> num_src_components_minus_one;
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BitField<24, 2, u32> num_dst_components_minus_one;
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};
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};
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static_assert(sizeof(RemapConst) == 12);
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explicit MaxwellDMA(Core::System& system, MemoryManager& memory_manager);
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~MaxwellDMA() = default;
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/// Write the value to the register identified by method.
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void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
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/// Write multiple values to the register identified by method.
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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private:
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/// Performs the copy from the source buffer to the destination buffer as configured in the
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/// registers.
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void Launch();
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void CopyPitchToPitch();
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void CopyBlockLinearToPitch();
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void CopyPitchToBlockLinear();
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void FastCopyBlockLinearToPitch();
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Core::System& system;
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MemoryManager& memory_manager;
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std::vector<u8> read_buffer;
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std::vector<u8> write_buffer;
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static constexpr std::size_t NUM_REGS = 0x800;
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struct Regs {
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union {
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struct {
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u32 reserved[0x40];
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u32 nop;
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u32 reserved01[0xf];
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u32 pm_trigger;
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u32 reserved02[0x3f];
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Semaphore semaphore;
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u32 reserved03[0x2];
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RenderEnable render_enable;
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PhysMode src_phys_mode;
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PhysMode dst_phys_mode;
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u32 reserved04[0x26];
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LaunchDMA launch_dma;
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u32 reserved05[0x3f];
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PackedGPUVAddr offset_in;
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PackedGPUVAddr offset_out;
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u32 pitch_in;
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u32 pitch_out;
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u32 line_length_in;
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u32 line_count;
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u32 reserved06[0xb8];
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RemapConst remap_const;
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Parameters dst_params;
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u32 reserved07[0x1];
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Parameters src_params;
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u32 reserved08[0x275];
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u32 pm_trigger_end;
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u32 reserved09[0x3ba];
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(launch_dma, 0xC0);
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ASSERT_REG_POSITION(offset_in, 0x100);
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ASSERT_REG_POSITION(offset_out, 0x102);
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ASSERT_REG_POSITION(pitch_in, 0x104);
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ASSERT_REG_POSITION(pitch_out, 0x105);
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ASSERT_REG_POSITION(line_length_in, 0x106);
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ASSERT_REG_POSITION(line_count, 0x107);
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ASSERT_REG_POSITION(remap_const, 0x1C0);
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ASSERT_REG_POSITION(dst_params, 0x1C3);
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ASSERT_REG_POSITION(src_params, 0x1CA);
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#undef ASSERT_REG_POSITION
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};
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} // namespace Tegra::Engines
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