207 lines
6.4 KiB
C++
207 lines
6.4 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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Id result{};
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if (IR::Inst* const carry{inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp)}) {
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const Id carry_type{ctx.TypeStruct(ctx.U32[1], ctx.U32[1])};
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const Id carry_result{ctx.OpIAddCarry(carry_type, a, b)};
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result = ctx.OpCompositeExtract(ctx.U32[1], carry_result, 0U);
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const Id carry_value{ctx.OpCompositeExtract(ctx.U32[1], carry_result, 1U)};
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carry->SetDefinition(ctx.OpINotEqual(ctx.U1, carry_value, ctx.u32_zero_value));
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carry->Invalidate();
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} else {
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result = ctx.OpIAdd(ctx.U32[1], a, b);
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}
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if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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if (IR::Inst* const sign{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)}) {
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sign->SetDefinition(ctx.OpSLessThan(ctx.U1, result, ctx.u32_zero_value));
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sign->Invalidate();
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}
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if (IR::Inst * overflow{inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
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// https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
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constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
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const Id is_positive{ctx.OpSGreaterThanEqual(ctx.U1, a, ctx.u32_zero_value)};
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const Id sub_a{ctx.OpISub(ctx.U32[1], ctx.Constant(ctx.U32[1], s32_max), a)};
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const Id positive_test{ctx.OpSGreaterThan(ctx.U1, b, sub_a)};
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const Id negative_test{ctx.OpSLessThan(ctx.U1, b, sub_a)};
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const Id carry_flag{ctx.OpSelect(ctx.U1, is_positive, positive_test, negative_test)};
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overflow->SetDefinition(carry_flag);
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overflow->Invalidate();
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}
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return result;
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}
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void EmitIAdd64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitISub32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U32[1], a, b);
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}
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void EmitISub64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIMul(ctx.U32[1], a, b);
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}
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Id EmitINeg32(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U32[1], value);
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}
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Id EmitINeg64(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U64, value);
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}
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Id EmitIAbs32(EmitContext& ctx, Id value) {
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return ctx.OpSAbs(ctx.U32[1], value);
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}
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Id EmitIAbs64(EmitContext& ctx, Id value) {
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return ctx.OpSAbs(ctx.U64, value);
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}
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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}
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Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U64, base, shift);
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}
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Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U32[1], base, shift);
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}
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Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U64, base, shift);
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}
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift);
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}
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Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
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}
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpBitwiseAnd(ctx.U32[1], a, b);
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}
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Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpBitwiseOr(ctx.U32[1], a, b);
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}
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Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpBitwiseXor(ctx.U32[1], a, b);
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}
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Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) {
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return ctx.OpBitFieldInsert(ctx.U32[1], base, insert, offset, count);
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}
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Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count);
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}
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Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
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if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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return result;
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}
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Id EmitBitReverse32(EmitContext& ctx, Id value) {
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return ctx.OpBitReverse(ctx.U32[1], value);
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}
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Id EmitBitCount32(EmitContext& ctx, Id value) {
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return ctx.OpBitCount(ctx.U32[1], value);
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}
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Id EmitBitwiseNot32(EmitContext& ctx, Id value) {
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return ctx.OpNot(ctx.U32[1], value);
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}
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Id EmitFindSMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindSMsb(ctx.U32[1], value);
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}
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Id EmitFindUMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindUMsb(ctx.U32[1], value);
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}
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Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMin(ctx.U32[1], a, b);
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}
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Id EmitUMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMin(ctx.U32[1], a, b);
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}
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Id EmitSMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMax(ctx.U32[1], a, b);
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}
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Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMax(ctx.U32[1], a, b);
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}
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1, lhs, rhs);
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}
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Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpULessThan(ctx.U1, lhs, rhs);
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}
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Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpIEqual(ctx.U1, lhs, rhs);
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}
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Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThanEqual(ctx.U1, lhs, rhs);
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}
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Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpULessThanEqual(ctx.U1, lhs, rhs);
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}
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Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
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}
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Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpUGreaterThan(ctx.U1, lhs, rhs);
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}
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Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpINotEqual(ctx.U1, lhs, rhs);
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}
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Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThanEqual(ctx.U1, lhs, rhs);
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}
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Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
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}
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} // namespace Shader::Backend::SPIRV
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