274 lines
10 KiB
C++
274 lines
10 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "video_core/engines/maxwell_3d.h"
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namespace Tegra {
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namespace Engines {
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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{0xE1A, {"BindTextureInfoBuffer", 1, &Maxwell3D::BindTextureInfoBuffer}},
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{0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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{0xE2A, {"BindStorageBuffer", 1, &Maxwell3D::BindStorageBuffer}},
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Maxwell3D::SubmitMacroCode(u32 entry, std::vector<u32> code) {
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uploaded_macros[entry * 2 + MacroRegistersStart] = std::move(code);
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}
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void Maxwell3D::CallMacroMethod(u32 method, const std::vector<u32>& parameters) {
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// TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
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// The requested macro must have been uploaded already.
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ASSERT_MSG(uploaded_macros.find(method) != uploaded_macros.end(), "Macro %08X was not uploaded",
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method);
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auto itr = method_handlers.find(method);
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ASSERT_MSG(itr != method_handlers.end(), "Unhandled method call %08X", method);
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ASSERT(itr->second.arguments == parameters.size());
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(this->*itr->second.handler)(parameters);
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// Reset the current macro and its parameters.
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executing_macro = 0;
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macro_params.clear();
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}
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void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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// It is an error to write to a register other than the current macro's ARG register before it
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// has finished execution.
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if (executing_macro != 0) {
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ASSERT(method == executing_macro + 1);
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}
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// Methods after 0xE00 are special, they're actually triggers for some microcode that was
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// uploaded to the GPU during initialization.
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if (method >= MacroRegistersStart) {
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// We're trying to execute a macro
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if (executing_macro == 0) {
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// A macro call must begin by writing the macro method's register, not its argument.
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ASSERT_MSG((method % 2) == 0,
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"Can't start macro execution by writing to the ARGS register");
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executing_macro = method;
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}
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macro_params.push_back(value);
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// Call the macro when there are no more parameters in the command buffer
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if (remaining_params == 0) {
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CallMacroMethod(executing_macro, macro_params);
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}
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return;
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}
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regs.reg_array[method] = value;
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#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
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switch (method) {
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case MAXWELL3D_REG_INDEX(code_address.code_address_high):
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case MAXWELL3D_REG_INDEX(code_address.code_address_low): {
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// Note: For some reason games (like Puyo Puyo Tetris) seem to write 0 to the CODE_ADDRESS
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// register, we do not currently know if that's intended or a bug, so we assert it lest
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// stuff breaks in other places (like the shader address calculation).
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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}
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[0]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[1]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[2]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[3]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[4]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[5]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[6]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[7]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[8]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[9]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[10]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[11]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[12]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[13]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[14]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[15]): {
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ProcessCBData(value);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Vertex);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[1].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationControl);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[2].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationEval);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[3].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Geometry);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[4].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Fragment);
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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break;
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}
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case MAXWELL3D_REG_INDEX(query.query_get): {
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ProcessQueryGet();
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break;
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}
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default:
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break;
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}
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#undef MAXWELL3D_REG_INDEX
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}
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void Maxwell3D::ProcessQueryGet() {
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GPUVAddr sequence_address = regs.query.QueryAddress();
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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// VAddr before writing.
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VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
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switch (regs.query.query_get.mode) {
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case Regs::QueryMode::Write: {
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// Write the current query sequence to the sequence address.
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u32 sequence = regs.query.query_sequence;
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Memory::Write32(address, sequence);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Query mode %u not implemented", static_cast<u32>(regs.query.query_get.mode.Value()));
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}
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}
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void Maxwell3D::DrawArrays() {
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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}
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void Maxwell3D::BindTextureInfoBuffer(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader stage, usually 4 for FragmentShader
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*/
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u32 stage = parameters[0];
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// Perform the same operations as the real macro code.
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GPUVAddr address = static_cast<GPUVAddr>(regs.tex_info_buffers.address[stage]) << 8;
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u32 size = regs.tex_info_buffers.size[stage];
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regs.const_buffer.cb_size = size;
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regs.const_buffer.cb_address_high = address >> 32;
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regs.const_buffer.cb_address_low = address & 0xFFFFFFFF;
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}
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void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader Program.
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* [1] = Unknown, presumably the shader id.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [3] = Shader Stage.
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* [4] = Const Buffer Address >> 8.
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*/
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auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]);
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// TODO(Subv): This address is probably an offset from the CODE_ADDRESS register.
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GPUVAddr address = parameters[2];
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auto shader_stage = static_cast<Regs::ShaderStage>(parameters[3]);
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GPUVAddr cb_address = parameters[4] << 8;
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auto& shader = state.shader_programs[static_cast<size_t>(shader_program)];
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shader.program = shader_program;
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shader.stage = shader_stage;
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shader.address = address;
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// Perform the same operations as the real macro code.
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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auto& shader_regs = regs.shader_config[static_cast<size_t>(shader_program)];
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shader_regs.start_id = address;
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// TODO(Subv): Write params[1] to register 0xD1C + shader_program.
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// TODO(Subv): Write params[2] to register 0xD22 + shader_program.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x10000;
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regs.const_buffer.cb_size = DefaultCBSize;
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regs.const_buffer.cb_address_high = cb_address >> 32;
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regs.const_buffer.cb_address_low = cb_address & 0xFFFFFFFF;
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// Write a hardcoded 0x11 to CB_BIND, this binds the current const buffer to buffer c1[] in the
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// shader. It's likely that these are the constants for the shader.
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regs.cb_bind[static_cast<size_t>(shader_stage)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_stage)].index.Assign(1);
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ProcessCBBind(shader_stage);
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}
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void Maxwell3D::BindStorageBuffer(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Buffer offset >> 2
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*/
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u32 buffer_offset = parameters[0] << 2;
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// Perform the same operations as the real macro code.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x5F00;
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regs.const_buffer.cb_size = DefaultCBSize;
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GPUVAddr address = regs.ssbo_info.BufferAddress();
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regs.const_buffer.cb_address_high = address >> 32;
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regs.const_buffer.cb_address_low = address & 0xFFFFFFFF;
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regs.const_buffer.cb_pos = buffer_offset;
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& bind_data = regs.cb_bind[static_cast<size_t>(stage)];
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auto& buffer = shader.const_buffers[bind_data.index];
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buffer.enabled = bind_data.valid.Value() != 0;
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buffer.index = bind_data.index;
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buffer.address = regs.const_buffer.BufferAddress();
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buffer.size = regs.const_buffer.cb_size;
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}
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void Maxwell3D::ProcessCBData(u32 value) {
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// Write the input value to the current const buffer at the current position.
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GPUVAddr buffer_address = regs.const_buffer.BufferAddress();
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ASSERT(buffer_address != 0);
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// Don't allow writing past the end of the buffer.
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ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
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VAddr address =
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memory_manager.PhysicalToVirtualAddress(buffer_address + regs.const_buffer.cb_pos);
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Memory::Write32(address, value);
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// Increment the current buffer position.
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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} // namespace Engines
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} // namespace Tegra
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