2013-09-18 03:03:54 +00:00
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/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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2014-07-23 23:16:40 +00:00
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2013-09-18 03:03:54 +00:00
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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2014-07-23 23:16:40 +00:00
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2013-09-18 03:03:54 +00:00
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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2014-07-23 23:16:40 +00:00
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2013-09-18 03:03:54 +00:00
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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2015-02-13 13:08:21 +00:00
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#include <cstring>
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2014-09-11 01:27:14 +00:00
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#include "core/arm/skyeye_common/armdefs.h"
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2015-04-18 00:44:54 +00:00
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#include "core/arm/skyeye_common/vfp/vfp.h"
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2013-09-18 03:03:54 +00:00
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/***************************************************************************\
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* Returns a new instantiation of the ARMulator's state *
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\***************************************************************************/
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2015-01-30 18:24:19 +00:00
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ARMul_State* ARMul_NewState(ARMul_State* state)
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2013-09-18 03:03:54 +00:00
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{
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2014-07-23 23:16:40 +00:00
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state->Emulate = RUN;
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2015-02-11 15:49:48 +00:00
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state->Mode = USER32MODE;
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2014-07-23 23:16:40 +00:00
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state->lateabtSig = HIGH;
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state->bigendSig = LOW;
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2015-01-30 18:24:19 +00:00
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return state;
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2013-09-18 03:03:54 +00:00
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}
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/***************************************************************************\
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* Call this routine to set ARMulator to model a certain processor *
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\***************************************************************************/
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2015-01-30 18:24:19 +00:00
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void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
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2013-09-18 03:03:54 +00:00
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{
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2015-04-18 00:44:54 +00:00
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
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state->is_v5 = (properties & ARM_v5_Prop) != 0;
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state->is_v5e = (properties & ARM_v5e_Prop) != 0;
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state->is_v6 = (properties & ARM_v6_Prop) != 0;
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state->is_v7 = (properties & ARM_v7_Prop) != 0;
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2013-09-18 03:03:54 +00:00
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}
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2015-04-06 13:12:55 +00:00
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// Resets certain MPCore CP15 values to their ARM-defined reset values.
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static void ResetMPCoreCP15Registers(ARMul_State* cpu)
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{
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// c0
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_MAIN_ID] = 0x410FB024;
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cpu->CP15[CP15_TLB_TYPE] = 0x00000800;
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cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
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cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
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cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
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cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011;
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cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111;
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cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011;
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cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131;
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cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141;
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2015-04-06 13:12:55 +00:00
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// c1
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_CONTROL] = 0x00054078;
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cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
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cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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// c2
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
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cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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// c3
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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// c7
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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// c9
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
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2015-04-06 13:12:55 +00:00
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// c10
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
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cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
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cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
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2015-04-06 13:12:55 +00:00
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// c13
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_PID] = 0x00000000;
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cpu->CP15[CP15_CONTEXT_ID] = 0x00000000;
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cpu->CP15[CP15_THREAD_UPRW] = 0x00000000;
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cpu->CP15[CP15_THREAD_URO] = 0x00000000;
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cpu->CP15[CP15_THREAD_PRW] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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// c15
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2015-04-06 16:43:23 +00:00
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cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
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cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
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2015-04-06 13:12:55 +00:00
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}
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2013-09-18 03:03:54 +00:00
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/***************************************************************************\
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* Call this routine to set up the initial machine state (or perform a RESET *
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\***************************************************************************/
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2015-01-30 18:24:19 +00:00
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void ARMul_Reset(ARMul_State* state)
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2013-09-18 03:03:54 +00:00
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{
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2015-04-18 00:44:54 +00:00
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VFPInit(state);
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2015-02-11 17:19:49 +00:00
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state->Reg[15] = 0;
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state->Cpsr = INTBITS | SVC32MODE;
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state->Mode = SVC32MODE;
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2014-07-23 23:16:40 +00:00
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state->Bank = SVCBANK;
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2015-04-06 13:12:55 +00:00
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ResetMPCoreCP15Registers(state);
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2014-07-23 23:16:40 +00:00
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state->NresetSig = HIGH;
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state->NfiqSig = HIGH;
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state->NirqSig = HIGH;
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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state->abortSig = LOW;
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state->NumInstrs = 0;
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2013-09-18 03:03:54 +00:00
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}
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